Xilinx demos emerging 400GE standard interoperability
Article By : EE Times India
Demonstrations include new 400G Ethernet, FlexE 1.0, and MACsec solutions to accelerate time to market and maximise scalability.
Xilinx is extending its offering of high-speed data centre interconnect (DCI) solutions to give systems OEMs maximum flexibility and enable migration to next-generation designs, while allowing for scalable performance at the lowest risk while ensuring network security.
Among the solutions is a standards-based 400GE MAC and PCS IP in a Xilinx Virtex UltraScale+ VU9P FPGA. At the OFC 2017 event in California, Xilinx demonstrated the emerging 400GE standard interoperability between multiple vendors using its 400G solution connected to a Finisar 400GE CFP8 module, which, in turn, is connected to a Spirent 400G test module.
Xilinx also demonstrated a complete FlexE 1.0 solution, showcasing bonding, sub-rating and channelisation on UltraScale+ FPGAs. This solution demonstrates how multiple clients can be transported using FlexE and highlights the ability of FlexE to carry larger data pipes and match them to transport links for optimal utilisation of the link budget, according to the company. This solution allows network operators to maximise optical performance and lower operating costs over existing infrastructure.
Another Xilinx demonstration showed how LLDP packets can be snooped on transport line cards to allow a SDN controller to build a network topology for automation integral to data centre networks. It also shows the use of IEEE compliant MACsec to encrypt and authenticate the link for security. As more and more critical applications and data migrate to the cloud, MACsec provides data encryption and authentication to preserve privacy. Such a solution is mandatory in front of a traditional DSP to provide a complete DCI solution.
Xilinx also showed how its FPGAs provide the required abstraction from differing technology integration by multiple manufacturers and enables designers to choose or mix optical technologies on a single platform. Meanwhile, a separate demonstrations showed Xilinx's new 56G PAM-4 transceiver test chip in 16nm FinFET delivering optimised performance for backplane and LR applications.