Test Access Opened to Every Die in 3D IC Stack
Article By : Nitin Dahad
3D stacked ICs will deliver next wave of innovation as the industry scales past 7nm. A standardized design for test (DfT) approach will help automated test access to each die layer.
The recently approved IEEE 1838 standard allowing consistent stack-level test access architecture to 3D integrated circuits (ICs) is to be included in the IEEE Xplore Digital Library from February 2020.
Heterogeneous integration using 3D-ICs allows designers to exploit the vertical dimension for further integration by stacking dies on top of each other, as an alternative way of overcoming the physical limitations of Moore’s Law in single process technologies. The standardization effort of the 3D-DfT (design-for-test), initiated by Imec, allows die makers to design dies which, if compliant to this standard and stacked in a 3D-IC by a stack integrator, enables consistent access to every layer in the stack, making testing using automatic test equipment much easier.
Eric Beyne, fellow and program director for 3D system integration at Imec, said, “Advances in wafer processing and stack assembly technologies are creating a wealth of different stack architectures. This causes a sharp increase in the number of potential moments at which testing for manufacturing defects can be executed: pre-bond (before stacking), mid-bond (on partial stacks), post-bond (on complete stacks), and final test (on packaged 3D-ICs).” He added that in a die stack, test equipment needs to access such ICs through an external interface or through probe needles or at test socket, but the external interface typically resides in the bottom die of the stack. “For the test equipment to be able to deliver test stimuli to and receive responses from the various dies up in the stack, collaboration from the underlying dies is required to provide test access to the die currently being tested.”
The new standard consists of three main elements to overcome this challenge:
(1) DWR, the die wrapper register: scan chains at the boundary of each die in the stack to enable modular testing of the internals of each die and of the interconnects between each pair of adjacent dies.
(2) SCM, the serial control mechanism: a single-bit test control mechanism that transports instructions into the stack to control the test modes of the various die wrappers.
(3) FPP, the optional flexible parallel port, i.e., a scalable multi-bit test access mechanism to efficiently transport up and down the die stack the large volumes of data typically associated with production test.
While DWR and SCM are based on existing DfT standards, Imec said it’s the FPP that is truly novel to IEEE Std 1838.
The IEEE working group to standardize 3D-DfT was founded in 2011 by Erik Jan Marinissen, scientific director at imec in Leuven, Belgium and he served as its first chair. In recent years, Adam Cron, principal R&D engineer in the design group at Synopsys, has been the driving force as the current chair of the working group. Amit Sanghani, vice president of engineering in the design group at Synopsys in Mountain View, California, U.S., said, “3D-IC is an important technology to deliver the next wave of innovation as the industry scales past 7nm. Currently, die might come from different suppliers with disjoint DfT architectures. We believe standardizing 3D-DfT will benefit our customers by helping form a consistent stack-level DfT architecture and speeding time to market. Synopsys congratulates the IEEE P1838 Working Group on this milestone.”
At Cadence Design Systems in San Jose, California, Wolfgang Meyer, its senior group director for R&D added, “A DfT standard like IEEE Std 1838 is important to the industry. Die makers know what they must provide, and stack integrators know they can expect. Moreover, EDA suppliers like Cadence can focus their tool support on architectures that are compliant with the new standard. It is good that there is some user-defined scalability with the standard as the 3D-IC field is so wide — a rigid ‘one-size-fits-all’ standard would not work.”
The manager of HiSilicon’s 150-person strong DfT team in Shenzhen, China, Junlin Huang, said, “Per year, we do DfT insertion and automatic test pattern generation (ATPG) for tens of very large and complex digital chip designs in the most advanced technologies. Now, these products start using 3D technology and my DfT team needs to be ready to handle the associated DfT and ATPG challenges. IEEE Std 1838 will help us with that task.”