Exploring Embedded DisplayPort

Article By : Craig Wiley

DisplayPort is the A/V interface developed and deployed by the personal computer industry through collaboration within VESA, providing display resolutions of 4K and beyond.

Today's personal electronic devices continue to get smaller and easier to use, with more performance and functionality. Such advances are often driven by technology hidden from the consumer, behind the sleek industrial design and elegant user interface. Video quality improvements are one example. A "better" display is normally equated to more pixels per inch driven by a multi-core GPU that supports high-resolution rendering. But "better" can also be one that uses less power to extend battery life, interferes less with wireless service to enable better coverage, and improves chip integration to enable sleeker, lighter-weight system designs.

VESA recently announced an update to the eDP Standard. Called eDP v1.4b, this new version puts the finishing touches on the eDP v1.4 Standard that was released in February 2013. Panels capable of supporting eDP v1.4b are now in production, and eDP v1.4b will be enabled in 2016 notebooks. eDP v1.4b includes several enhancements to enable improved flexibility of system implementation, reduced device complexity and lower bill of materials (BOM) costs. However, before we get into what's new for eDP v1.4b, let's look back at why the eDP Standard was first developed, and how it has affected the electronics ecosystem through the collaborative efforts of VESA member companies that continually evolve this standard and propagate it across the supply chain.

__Figure 1:__ *At display resolutions beyond Full HD (1920×1080) or Full HD+ (1920×1200), eDP has a significant advantage over LVDS in minimizing the number of high-speed wire pairs needed in the display interface, which in turn results in reduced total system footprint. (Source: VESA)*

Creating the foundation for eDP
eDP was first introduced in late 2008 as a simplified version of DisplayPort for internal displays. The main goal was a common display interface that could be used for both external and internal displays. Shortly thereafter, the main GPU / CPU vendors, including Intel, NVIDIA and AMD, announced that eDP would replace the current (at that time) LVDS interface standard, and that LVDS support would go away, which it now has. The motivation was simple: The chip industry needed to replace the high-voltage LVDS interface with one that could drive integration and display performance. eDP became the obvious choice because it could repurpose the flexible and extensible DisplayPort interface—meaning the same video port could drive an internal or external display, enabling platform application and design flexibility.

Through subsequent releases of the eDP standard over the last several years, the computer industry OEMs involved with the standard have continued to make refinements unique to eDP and not shared by DisplayPort, at least not at the time. eDP v1.0, which was released in 2008, was basically a simplified version of DisplayPort with a definition of panel power sequencing. In late 2009, eDP v1.1 added system power management enhancements through the introduction of video frame rate control. One of those particular methods later became the Adaptive-Sync feature, now supported by DisplayPort (figure 2). This was followed by the release of eDP v1.2 in 2010 with a new set of commands sent over the AUX Channel—the sideband bus used for both DisplayPort and eDP—to control other aspects of the display, including backlight brightness and color rendering characteristics. This eliminated the need for other control signals, removing several pins and wires in the display interface. And then in eDP v1.3, published in early 2011, new display protocols were added to enable Panel Self Refresh (PSR), which adds a separate frame buffer to the display and allows the host GPU / CPU to enter a low power state when a static display image is encountered, which is surprisingly often. This feature further reduces power and extends battery life.

__Figure 2:__ *Application of Adaptive-Sync to frame rate reduction (top); application of Adaptive-Sync to game rendering (bottom). (Source: Parade Technologies; galloping-horse photos by Eadweard Muybridge, 1887)*

Recent eDP developments focused on power reduction

Following eDP v1.3, which is commonly used for systems currently in production, eDP v1.4 was introduced in February 2013. eDP v1.4 included many new eDP-specific enhancements targeting further power reduction. One such feature is the partial frame update capability for PSR (PSR2). When the system is displaying a static image in self-refresh mode, such as text, and then just a portion of the image changes, such as the flashing cursor, partial frame update enables the GPU to only send that part of the image instead of the whole video frame (Figure 3). Another important and complementary upgrade is the ability to change the GPU power state more quickly. Enabling the GPU/CPU to quickly exit and enter the low-power state to make a selective image update saves system power.

__Figure 3:__ *Comparison between Panel Self Refresh (PSR) and PSR2 (updated version) operation. (Source: Parade Technologies)*

eDP v1.4 was also the first video interface standard to leverage a form of display stream compression. This new category of image compression enables the reduction of bit rate and wire count on the video interface, saving power and reducing form factor. It can also be used to reduce the display's frame buffer size, reducing BOM cost. And eDP v1.4 expanded backlight control to regional backlight control to enable further power savings. Power was also reduced in the high-speed electrical interface that carries the video data. By adding more flexibility in voltage swing and data transport rate, the interface can be better optimized for the system design and display requirements.

Refining the standard
Since the publication of eDP v1.4 over two years ago, the PC OEMs working within VESA have continued to refine the standard and have been working toward production beginning in 2016. This led to the publication of the eDP v1.4a release in early 2015. Two influences for this updated release were the publication of the VESA Display Stream Compression (DSC) Standard v1.0 in March 2014, which was an improvement over the compression standard used in eDP v1.4, and the publication of DisplayPort Standard v1.3 in September 2014. Both of these new standards came after the release of eDP v1.4 in February 2013 and contributed important enhancements to eDP v1.4a. For example, the 8.1Gbps link rate defined in DisplayPort v1.3, coupled with DSC, enables 8K display resolution support.

eDP v1.4a also added Multi-SST Operation (MSO) to support a segmented panel display architecture (Figure 4). This enables a higher level of integration on high-resolution displays, allowing integration of the panel timing controller with source drivers, enabling thinner, lighter displays with a lower BOM cost. eDP v1.4a also added Y-coordinates to the PSR2 partial update command, relaxing time-base accuracy requirements in the display and thereby eliminating the crystal or crystal oscillator requirement originally required for an eDP v1.4 display – again, further lowering system BOM cost.

__Figure 4:__ *The eDP v1.4a specification supports Segmented Panel display architectures, which are designed to enable thinner, lighter and lower-cost panels that use less power. (Source: VESA, photo by Craig Wiley)*

What's new in eDP 1.4b
With so many new enhancements in eDP v1.4 and eDP v1.4a, OEMs developing the eDP v1.4 products later discovered some vagueness and ambiguities in this committee-generated standard, as well as a few conflicts with DisplayPort v1.3. eDP v1.4b began as an effort to update the standard with clarifications and corrections agreed upon within VESA, to promote interoperability among member companies, and to minimize time to market. But eDP v1.4b also ended up incorporating a few other agreed-upon enhancements proposed by some of the member companies involved.

In particular, the selective update feature for panel self-refresh received many refinements and clarifications in protocol. Selectable granularity for the update region was also added to help reduce the complexity of the internal frame buffer storage. Many panel timing controllers use image compression, including DSC, for frame buffer storage. Limiting the X and Y axis granularity of the update region simplifies the compression codec implementation and lowers BOM cost.

The AUX Frame Sync requirement was also eliminated for PSR2 if selective updates are not used, meaning that frame buffer updates are made a full frame at a time. This eliminates the need to support both the DisplayPort GTC (Global Time Code) and AUX Frame Sync features, allowing more scalability of the PSR2 function. Cost can be reduced in exchange for a little less power savings. For MSO, additional cyclic redundancy check (CRC) registers were added to enable the verification of data integrity for the transport of video to each panel segment, up to the four display segments allowed.

Other small adjustments to eDP v1.4b include the removal of a few control register conflicts with DisplayPort v1.3 and clarification and refinement of other various protocols and operational sequences. With this final cleanup, the VESA members generally agreed that eDP v1.4b is the final release of the eDP v1.4 standard and that it is ready for production.

Made possible with DisplayPort
The ongoing enhancements to eDP v1.4b have been made possible by the flexible nature of DisplayPort. DisplayPort is highly extensible and includes the ability to remain backward compatible. An extensive register set is implemented in the sink (display) device to support both new and old features, and other registers indicate device status and allow control by the source. Data packets in the high-speed video interface include pixel data and other various control data. The VESA member companies developing the eDP ecosystem have added the special features described in this article using these DisplayPort features. This will continue, and there is already discussion about a future eDP v1.5 that will utilize the features of DisplayPort v1.4, recently published in February 2016.

Key features carried over from DisplayPort v1.4 will include FEC (Forward Error Correction) for the video link, which is important when employing video compression using DSC. FEC addresses data errors, which in an uncompressed image can result in an unnoticeable change of a single pixel, but with compression can result in a visible change across a whole block of pixels from a single error. Another feature brought over from DisplayPort v1.4 will be the ability to carry High Dynamic Range (HDR) metadata, allowing eDP to serve as an embedded interface for HDR-enabled displays. This will include support for the current HDR10 standard used in Blu-ray and HDMI 2.0b, and future support for more advanced HDR formats that will use extended metadata. However, until the publication of eDP 1.5, the VESA eDP v1.4b Standard will serve as the governing specification for embedded displays within PCs and other devices over the next few years.

It's important to emphasize that successful implementation and adoption of standards like DisplayPort and eDP would not be possible without the cooperative efforts of the more than 230 VESA members across the electronics supply chain. All VESA members have equal access to all work groups, proposals, and draft specifications. Typically, the organization holds about 10 different work group meetings per week, covering various VESA standards, and has two or more PlugTests per year open to all members. By participating in this manner, member companies – ranging from software, chip and display makers to consumer, communication and computing product OEMs – are able to better understand each other's concerns and challenges, facilitating mutually beneficial development efforts.

About the author
Craig Wiley has over 35 years in the semiconductor industry focused on analog, mixed-signal, video, and video interfaces primarily in the realm of applications and technical marketing. He serves as the main editor for the VESA Embedded DisplayPort Standard, and contributor to the DisplayPort Standard since 2007. He also serves on VESA Board of Directors, and served as Board Chair during 2011-2013. He is the leader of VESA Marketing Task Group, and DisplayPort on USB-C subgroup.