Dual DRAM controller core delivers 4,266MT/s

Article By : EE Times India

Designed in Ahmedabad, Gujarat, the dual DRAM Controller Core for LPDDR3 and LPDDR4 follows the JEDEC standards and is compatible with DFI3.1/4.0 PHY or a PHY from any vendor.

Arastu Systems, a company that specialises in developing IPs in the memory and networking area, has rolled out a dual DRAM Core for LPDDR3 and LPDDR4 that delivers up to 4,266MT/s performance.

Designed in Ahmedabad, Gujarat, the dual DRAM Controller Core follows the JEDEC standards and is compatible with DFI3.1/4.0 PHY or a PHY from any vendor. It supports all key LPDDR3/4 features such as various frequency ratios, programmability to achieve minimum latency, multiple channels with a privilege to configure each channel independently, multiple power down modes and parameterised data widths, among other things.

Arastu said SoC designers who are planning to run the design at multiple speeds can leverage the LPDDR3/4 IP core, which supports wide range of system application using the same design. The user can configure the IP core by parameter for LPDDR3/4, based on which the hardware for the controller is generated.