First Core with RISC-V Vector Instruction Extension Delivered
Andes’ new processor cores enable scalability by delivering RVV instruction extension and new memory subsystem. The company claims to be…
UltraSoC Donates Trace Encoder
Having the encoder available should help minimize the possible risk for potential RISC-V developers.
Can Carbon Nanotubes Take Us Beyond Silicon?
MIT's work on carbon nanotube field-effect transistors validates a promising path towards practical beyond-silicon electronic systems.
Qualcomm is the Newest Investor in SiFive
RISC-V is heading for mobile. Qualcomm participated in SiFive's $65.4m funding round. We talked CEO Naveed Sherwani recently about the…
RISC-V: A Boon for Military and Aerospace
RISC-V is getting attention from just about every vertical market, but it offers a number of particular benefits for military/aerospace…
Can SiFive Revive the Semiconductor Industry?
Today, most of SiFve’s customers just buy IP. But in five years, he believes that as many as two-thirds of…
Open-Silicon & SiFive to Chisel RISC-V in India
The fact that this open architecture has the capacity to bring custom silicon to all inventors and makers will benefit…
Krste Asanović : RISC-V Momentum is Massive in India
Indigenous microprocessor on RISC-V ISA, “Shakti” leads the way
RISC-V Boots Linux at SiFive
Startup SiFive has taped out and started licensing a version of the RISC-V core that runs Linux, expanding its set…