Verifying the true jitter performance of clocks in high-speed digital designs - EE Times India
Verifying the true jitter performance of clocks in high-speed digital designsAs the data rates in high-speed digital designs increase, the limits for overall system jitter become tighter. This especially applies to the various components of the clock tree, where the jitter limits for reference clocks, clock buffers and jitter attenuators are even tighter. Due to […]
