Synopsis tangoes to M&A tune for software security
Synopsis has signed a merger deal with Cigital and Codiscope, both software security experts, as the former makes another bid…
Cadence, Mathworks tieup on IoT simulation
The partnership may help integrate Simulink, a multi-domain environment for dynamic systems and PSpice, a SPICE-based simulator for mixed-signal circuits.
Tool upgrades boost PCB design process efficiency
Altium Designer 17 offers PCB layout design with guided routing technology, while Altium Vault 3.0 offers more control over data…
Samsung certifies Cadence tools for 10nm process
The Innovus Implementation System enables larger designs and reduced turnaround time while supporting Samsung’s 10LPP design requirement.
Modulator improves recording quality of green microphones
Green microphones fill the low-power gap by dividing by a ratio of at least 5 the power consumption in always-listening…
Linaro enhances API support for software-defined dataplane
The Monarch Long Term Support release of OpenDataPlane (ODP) enables other projects to leverage the acceleration provided by the ODP…
Facebook attracts EEs with hardware lab
The social networking company is expanding its horizons with a 2,000-square-metre hardware lab.
Verification IP for Ethernet 200G supports 8x25G interface
Synopsys VIP uses a native SystemVerilog/UVM architecture and features built-in comprehensive coverage and verification planning.
Processor subsystem verification: UVM
UVM, which produces random address for every transaction, is best suited for stress testing.
Processor subsystem verification: Directed verification
Assembly/C test cases are written to access all subcomponents and their registers like timer, SPI, I2C.